1. Field
Embodiments of the inventive concept relate to a phase locked loop (PLL) circuit configured to compensate for variations in oscillation frequency as a result of, e.g., leakage current, so as to maintain the oscillation frequency at a constant level, and a system having such a PLL circuit.
2. Description of the Related Art
A phase locked loop (PLL) circuit, which is a typical basic circuit employed in electronic systems, may generate an output clock signal having a desired frequency and may transmit the output clock signal to internal circuits. A PLL circuit may be included in various circuits configured to operate in synchronization with a clock signal. The PLL circuit may continuously compare a phase of the output clock signal with a phase of a reference clock signal to adjust a frequency of the output clock signal. So, the output clock signal can maintain a predetermined frequency.